The present invention relates to a semiconductor device, and particularly to a technique which is effective in an application thereof to a semiconductor device having a capacitance element.
Various semiconductor devices are produced by forming a MISFET, a capacitor, etc. over a semiconductor substrate and by wiring respective elements with wirings. The capacitors formed over the semiconductor substrate include a MOS type capacitance element, a PIP (Poly-silicon Insulator Poly-silicon) type capacitance element, an MIM (Metal Insulator Metal) type capacitance element, etc.
Japanese patent laid-open No. 2005-197396 (Patent document 1) discloses a technique to form a capacitance using a comb-shaped wiring.
Japanese patent laid-open No. 2006-253498 (Patent document 2) discloses a technique to connect a dummy pattern disposed neighboring a signal wiring pattern to a fixed potential such as a power source or the ground.
Japanese patent laid-open No. 2001-274255 (Patent document 3) discloses a technique to connect some of dummy wirings to a fixed potential node of a power source or the ground.
Japanese patent laid-open No. 2007-81044 (Patent document 4) discloses a technique to provide a shielding conductor so as to surround a capacitance element in a planar manner in the same wiring layer as that of an electrode of the capacitance element.